The present invention relates to a semiconductor device, and more particularly, the present invention relates to a semiconductor device having a high-voltage transistor.
A semiconductor device may include a memory cell array including a plurality of memory cells configured to store data and a plurality of peripheral circuits configured to program or erase data into or from the memory cells or read out data stored in the memory cells.
The peripheral circuits may include a plurality of page buffers coupled to the memory cell array through bit lines. The page buffers may provide a program permission voltage or a program prohibition voltage through the bit lines in a program operation and receive states of cells through the bit lines in a read operation.
Meanwhile, interference may occur between adjacent bit lines as a degree of integration of a semiconductor device increases. Thus, in order to prevent the interference, the bit lines are classified into even-numbered bit lines and odd-numbered bit lines. The even-numbered bit lines may be called even bit lines, and the odd-numbered bit lines may be called odd bit lines. Since each of the page buffers is coupled to a bit line pair including an even bit line and an odd bit line, each of the page buffers may include a bit line selection circuit configured to select the even bit line or and the odd bit line of the bit line pair.
FIG. 1 is a cross-sectional view of a conventional semiconductor device. Referring to FIG. 1, an isolation region IS is formed to define active regions AT in a semiconductor substrate 10 and filled with an insulating material 14. Gate lines of transistors TR are formed on the active region AT in the semiconductor substrate 10, and junction regions 12 are formed in the semiconductor substrate 10 adjacent to both ends of each of the gate lines. Thus, the transistors TR including the gate lines and the junction regions 12 are formed. After that, an interlayer insulating layer 17 is formed to cover a resultant structure including the transistors TR, and contact plugs CP are formed on the junction regions 12 to penetrate the interlayer insulating layer 17. Each of bit lines BLo and BLe is formed over the interlayer insulating layer 17 to be coupled to each of the contact plugs CP.
When high-voltage transistors are formed in a selection circuit region and different voltages are applied to junction regions 12 formed in different active regions AT, depletion may occur in a region between the junction regions 12 in the different active regions AT. To prevent the occurrence of the depletion, an ion implantation process may be performed onto a portion of the semiconductor substrate 10 disposed under the isolation region IS, thereby forming a field stop ion implantation region FS. The field stop ion implantation region FS may be formed by implanting impurities having a different type from that of the junction region 12 formed in the active region AT. Accordingly, if a distance between the field stop ion implantation region FS and the junction region 12 is excessively reduced, a breakdown (BD) voltage may be lowered. To prevent this phenomenon from occurring, a minimum distance between the field stop ion implantation region FS and the junction region 12 should be secured. As a result, an area occupied by a semiconductor device may increase depending on a width W of the field stop ion implantation region FS and the minimum distance between the field stop ion implantation region FS and the junction region 12.